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STRUCTURE PRODUCTSERIES TYPE
FEATURES
Silicon Monolithic Integrated Circuit 2-ch Switching Regulator Controller
BD9848FV
High Input-voltage ( Vcc=35V) MOSFET-driver circuit built-indual circuit for step-down output Built-in circuits for error amplifier reference voltage (1.0 V1%) 5 consecutive over current pulse detection circuit built in. Soft-start timing adjustable Master/Slave function Absolute maximum ratingsTa=25 Item Symbol Vcc Pd VOUT VC5V Topr Tstg Tjmax Limits 36 8121 Vcc-7VVcc Vcc-7VVcc -40+105 -55+150 150 Unit V mW V V
Power Supply Voltage
Power dissipation Output pin voltage C5V pin voltage Operating temperature Storage temperature
Maximum Junction temperature Recommended operating range (Ta=25) Item Symbol Power Supply Voltage
Output pin voltage Error amplifier input voltage Timing capacitor Oscillation frequency Vcc VOUT INV CCT
*1 Should be deleted by 6.5mW/ at Ta=25 or more. When mounted on a glass epoxy PCB of 70.0mmx70.0 mmx1.6 mm
Min.
3.6 C5V 0 47
Typ.
6.0 -
Max.
35 Vcc VREF-0.9 3000
Unit V V V pF kHz V V V V V
100 1500 fosc 0 VCC VSTB STB input voltage 0 VREF+0.3 DT DT input voltage Vcc-0.2 Vcc+0.2 VOCP OCP+/- input voltage CTexternal oscillation waveform 1.9 2.3Item
VREF output block VREF output voltage Line regulation Load regulation Output max. current
Symbol
Limits
Min.
2.475 2
Typ.
2.500 1 2 13
Max.
2.525 10 10
Unit
Conditions
VREF Line reg. Load reg. IOMAX
V mV mV mA
IO=0.1mA Vcc=3.6V35V IO=0.1mA2mA VREF=(typ.)0.95
REV. C
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Electrical characteristics (Unless otherwise specified, Ta=25VCC=6V)
Item
Triangular wave oscillator block
Symbol
Min. 95 1.4 5 1 3.0 0.99 70 2.30 0.5 50 1.4 1.9 4.5 0.04 0.8 1.1 0 2.4 3 1.5
limits Typ. 106 0 2 12 0.1 3.3 3.2 0.15 1 1 0 85 0.6 1.5 105 1.5 2 4 3.3 5 0.05 0.1 200 1.6 1.25 2.5 70 0 3
Max. 117 1 2.6 1 3.4 0.25 1.01 6 1
VREF
Unit
Conditions
Oscillation frequency
Frequency variation
fOSC fDV ISSSO ISSSI
kHz % A mA A mA V V V mV A dB V V mA A V V V V A nS mS V V V V A A mA
CCP=1800pF Vcc=3.6V35V SS=0.5V SS=0.5V DT=1.75V DT=1.75V, (OCP+)-(OCP-)=0.5V
Soft-start block
SS pin source current SS pin sink current
Dead time adjustable circuit block IDT DT pin input bias current IDTSI DT pin sink current
UVLO block
Threshold voltage
Hysterisis Error Amp block
VUTH VUHYS
Vcc when rise time
Non-Inverting
input
reference
VINV dVinv IIB AV VFBH VFBL IFBSI IFBSO Vt0 Vt100 RONH RONL VCLMP
VOCPTH
INV=FB Vcc=3.6V35V INV=1V
Reference voltage variation INV input bias current Open loop gain Output FB voltage (Hi)
Output FB voltage (Low)
Output sink current Output source current PWM comparator Input threshold voltage fosc=100kHz Output block Output ON resistance H Output ON resistance L C5V clamp voltage
1.3 1.6 2.1 10 10 5.5 0.06 10 400 1.4 0.5 2.6 VCC 100 1 6
FB=1.25V , INV=1.5V FB=1.25V , INV=0V On duty 0% On duty 100% RONH=( VCC -OUT)/ Iout, Iout=0.1A RONL=(OUT-C5V)/ Iout, Iout=0.1A VCLMP= VCC-C5V , VCC 7V Voltage between (OCP+)-(OCP-) OCP+= VCC, OCP-= VCC-0.05V OCP-= VCCVCC-0.2V OCP-= VCC-0.2VVCC DT Pin H/L
Over current protection circuit (OCP) block
OCP threshold voltage
OCP-input bias current Delay time for OCP Min. hold time for OCP Stand-by switch block Threshold voltage for each CH stop Stand-by mode setting voltage range Slave mode setting voltage range
Active(Master) mode setting voltage range
IOCPtdocpth tdocpre
VDTthL VSTBL VSTBM VSTBH ISTB ICCS ICCA
STB current Total device
STB=6V STB=0V INV=0V, FB=H, DT=1.75V
Stand-by current
Average current consumption Not designed for radiation resistance.
REV. C
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Outline figure
PIN No./ name / function
Pin No .
1
Pin name
CT DT2 SS2 INV2 FB2 GND OCP2 OCP2 C5V OUT2 OUT1 Vcc OCP1 OCP1 STB FB1 INV1 SS1 DT1 VREF
Pin function
External Capacitor pin for timing change Dead time setting (CH2) Soft-start time setting (CH2) Error Amp inverting input (CH2) Error Amp output (CH2) GROUND Over current error amp inverting input (CH2) Over current error amp input (CH2) Output L voltageVcc-5V CH2 Output CH1 Output Power supply input Over current error amp input (CH1)
type
2 3 4
BD9848
5 6 7 8 9
1 pin Mark
Lot NO.
10 11 12 13 14 15
Over current error amp inverting input (CH1) Stand-by mode control Error Amp output (CH1) Error Amp inverting input (CH1) Soft-start time setting (CH1) Dead time setting (CH1) Reference voltage2.5Voutput
SSOP-B20 (Unit : mm)
16 17 18 19
Block Diagram
20
VCC
VCC
Refer p.4 Operation note(9)
STB
OCP1+ OCP1-
VCC VREF VCC
VREF
REG (2.5V)
STB
VREF
OCP1
5pulse
OCP
+ C5V C5V 50mV10mV
REG (VCC-5V) C5V
DT1
DT1OFF
FB1
VREF 2A
DT +
1.25V
DT1Low
1V10mV
VCC
SS1
SS1OFF
+ + ERR -
+ + PWM -
LS
DRV
OUT1
C5V
INV1 OSC
200A + 200A
PROTECTION LOGIC
OCP1 2.0V 1.5V Hold time (1.6msec)
DT1Low
SS1OFF
DT1OFF
TSD
TSD
UVLO TSD Hold time (0.2msec) VCC VREF OCP2 Hold time (1.6msec) DT2Low SS2OFF DT2OFF C5V 3.2V 2.2V 3V
2V 1.5V
UVLO
UVLO
CT
INV2
VREF 2A
VCC
SS2
SS2OFF 1V10mV
+ ERR +
+ PWM +
OCP2 DT2Low
LS
DRV
OUT2
VCC
FB2 DT2
DT2OFF
DT +
1.25V
5pulse
OCP
C5V
50mV10mV
C5V
+
Operation Notes
OCP2+ OCP2GND
REV. C
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1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. 3) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 5) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. 7) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 8) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 9) Over Current Protection The OCP circuit is designed to be very sensitive circuit for protection of an application device. Therefore, it may detect ringing noises besides the true current signal. This depends on an application circuit and a layout pattern. In this case, the OCP current value is lower than the designed value. For the measure of this, please use CR filter on OCP input referring the circuit of the technical note. 10) General Please refer the technical note on designing. 11) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in Fig. 10, The P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins.
Resistance (PinA) (PinB)
Transistor (NPN)

(PinA) Parasitic diode

(PinB)

P substrate
P substrate
Parasitic diode
Parasitic elements Other adiacent components
Parasitic diode
REV. C
Notice
Notes
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